The present invention relates to a MOS semiconductor memory device, and particularly to a data read circuit therefor.
An asynchronous EPROM (electrically programmable read-only memory) having silicon gates known in the art is a NOR-type memory cell array shown for example in ISSCC 88 (1988 IEEE International Solid-state Circuits Conference) Session X, THAM 10.1 and THAM 10.2.
A circuit for assisting a memory cell array of the X-cell scheme (shared-contact configuration) which has X-cell configuration, different from the NOR-type configuration, and which can reduce the area for the memory cell array is shown for example in U.S. Pat. No. 4,387,447. The memory cell array of the X-cell scheme has the possibility of the size reduction of the memory cell array itself, and promises its utilization.
However, in the case of the X-cell scheme, circuits necessary for writing and reading data into and from the memory cell array are larger and more complicated than in the case of the NOR-type memory, and the area for the overall circuitry is larger, and the designing of the device is time-consuming. That is, in the case of the conventional X-cell scheme, shown for example in U.S. Pat. No. 4,722,075, the source lines and the data lines are disposed alternately in the column direction, and charging transistors for setting the source lines under a constant-bias condition when the memory cells are not selected, and switching transistors for lowering the potential on the source lines when the memory cells are selected, must be separately provided for the respective source lines. In the case of the NOR-type, only one MOS transistor is needed for each data line for selectively connecting the data lines to a common data line. Accordingly, the area for the circuits required is larger in the X-cell scheme than in the NOR-type.
Moreover, in the case of the conventional X-cell scheme, a bias circuit for setting the data line under the constant bias condition when the memory cells are not selected is formed of a circuit separate from the generator circuit for generating the data detect voltage provided for the sense amplifier. But because of the manufacturing variation in the characteristics of the transistors forming the integrated circuit, differences are created between the voltage on the data line due to the bias circuit and the voltage on the data line due to the sense amplifier, and it was necessary to allow the voltage on the data line selected during the data reading to change from the voltage due to the bias circuit to the data detect voltage. The time for reading data in the integrated circuit is therefore lengthened. Moreover, because of the manufacturing variation in the characteristics of the transistors forming the bias circuit for the data lines, the voltages on the source lines are not uniform and the time for reading data lines may not be uniform.
A further problem common to the conventional memories of the X-cell scheme and NOR-type is that the high voltage amplitude required of the data lines delays the data reading. That is, for example the voltage on the data line must be lower than the common data line in order to convey the current that flows through the memory element, from the data line to the common data line via a MOS transistor that connects the data line and the common data line. The data line must therefore be supplied with a signal having a voltage amplitude dependent on the source-drain resistance of the MOS transistor to achieve data reading. In the case of an ordinary EPROM, the source-drain resistance of the MOS transistor is on the order of 1 K.OMEGA., and the current amplitude dependent on the data on the memory element is 0 to 60 .mu.A, so a voltage having an amplitude of about 60 mV must be applied to the data line regardless of the performance of the sense amplifier. The necessity of the high voltage amplitude on the data line led to delay in the data reading from the integrated circuit.